Method of making printed wiring board and method of forming plating film

ABSTRACT

A current is supplied to first and second electrically-conductive resistances located away from each other on a straight line defined on an electrically-insulating substrate in a method of making a printed wiring board. A contour of the substrate is formed along the straight line based on the detected resistance values. The method allows an increase in the resistance values of the first and second electrically-conductive resistances in response to reduction of the first and second electrically-conductive resistances, respectively. The resistance values are thus utilized to determine the contour of the electrically-insulating substrate. Any process of defining the contour can be finished based on the determination of the contour. This enables establishment of the contour as designed with a higher accuracy.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of making a printed wiring board such as a small-sized printed wiring board for a chip package.

2. Description of the Prior Art

A printed wiring board is positioned relative to a chip when the chip is mounted on the printed circuit board in a chip package. In general, a camera is utilized for positioning the printed wiring board. Given marks are inscribed on the chip and the printed wiring board. The printed wiring board can be positioned relative to the chip based on the marks in images captured with the camera.

The marks cannot always be positioned with high accuracy. For example, electrically-conductive pads for receiving bumps of the chip sometimes shift relative to the mark on the printed wiring board. A larger shift of the mark causes the electrically-conductive pads on the printed wiring board to receive wrong bumps of the chip. The density of the bumps or connecting terminals cannot further be improved. A mounting efficiency cannot be enhanced.

SUMMARY OF THE INVENTION

It is accordingly an object of the present invention to provide a method of making a printed wiring board greatly contributing to improvement in the mounting efficiency. It is an object of the present invention to provide a method of forming a plating film greatly contributing to realization of such a method.

According to a first aspect of the present invention, there is provided a method of making a printed wiring board, comprising: supplying a current to first and second electrically-conductive resistances located away from each other on a straight line defined on an electrically-insulating substrate; detecting the resistance values of the first and second electrically-conductive resistances based on the supplied current; and forming a contour of the substrate along the straight line based on the detected resistance values.

The method allows an increase in the resistance values of the first and second electrically-conductive resistances in response to reduction of the first and second electrically-conductive resistances, respectively. The resistance values are thus utilized to determine the contour of the electrically-insulating substrate. Any process of defining the contour can be finished based on the determination of the contour. This enables establishment of the contour as designed with a higher accuracy.

The first and second electrically-conductive resistances are preferably contoured in an identical shape prior to the formation of the contour. The identical shape of the first and second electrically-conductive resistances leads to an easier establishment of conformance of the resistance values. The contour of the substrate can be determined in a relatively facilitated manner based on the conformance of the resistance values.

For example, the resistance value of the first electrically-conductive resistance may be compared with a predetermined reference value in the determination of the contour. If the resistance value is set equal to the reference value, the contour can reliably be set as designed in the substrate.

According to a second aspect of the present invention, there is provided a method of making a printed wiring board, comprising: supplying a current to first and second electrically-conductive resistances located away from each other on a first straight line defined on an electrically-insulating substrate; detecting the resistance values of the first and second electrically-conductive resistances based on the supplied current; forming a first contour of the substrate along the first straight line based on the resistance values from the first and second electrically-conductive resistances; supplying a current to third and fourth electrically-conductive resistances located away from each other on a second straight line orthogonal to the first straight line defined on the electrically-insulating substrate; detecting the resistance values of the third and fourth electrically-conductive resistances based on the supplied current; and forming a second contour of the substrate along the second straight line based on the resistance values from the third and fourth electrically-conductive resistances.

The method allows an increase in the resistance values of the first and second electrically-conductive resistances or the third and fourth electrically-conductive resistances in response to reduction of the first and second electrically-conductive resistances or the third and fourth electrically-conductive resistances, respectively. The resistance values are thus utilized to determine the first and second contours of the electrically-insulating substrate. Any process of defining the first and second contours can be finished based on the determination of the contours. This enables establishment of the first and second contours as designed with a higher accuracy.

The first and second electrically-conductive resistances are preferably contoured in an identical shape prior to the formation of the first contour. The identical shape of the first and second electrically-conductive resistances leads to an easier establishment of conformance of the resistance values. The contour of the substrate can be determined in a relatively facilitated manner based on the conformance of the resistance values. Similarly, The third and fourth electrically-conductive resistances are preferably contoured in an identical shape. All the first to fourth electrically-conductive resistances may have an identical shape.

For example, the resistance values of the first and third electrically-conductive resistances are compared with predetermined reference values, respectively, in the determination of the first and second contours. If the resistance values are set equal to the reference values, respectively, the first and second contours can reliably be set as designed in the substrate.

The above-described method serves to provide a specific printed wiring board. The printed wiring board may include: an electrically-insulating substrate having first and second contours defined along imaginary planes orthogonal to each other: an electrically-conductive terminal pad formed on the substrate; a first electrically-conductive resistance formed on the substrate along the first contour; a pair of first electrically-conductive pad formed on the substrate, the first electrically-conductive pads connected to the first electrically-conductive resistance; a second electrically-conductive resistance formed on the substrate along the first contour away from the first electrically-conductive resistance; a pair of second electrically-conductive pad formed on the substrate, the second electrically-conductive pads connected to the second electrically-conductive resistance; a third electrically-conductive resistance formed on the substrate along a second contour; a pair of third electrically-conductive pad formed on the substrate, the third electrically-conductive pads connected to the third electrically-conductive resistance; a fourth electrically-conductive resistance formed along the second contour away from the third electrically-conductive resistance on the substrate; and a pair of fourth electrically-conductive pad formed on the substrate, the fourth electrically-conductive pads connected to the fourth electrically-conductive resistance. Here, the resistance value of the first electrically-conductive resistance detected out of the first electrically-conductive pads is set equal to the resistance value of the second electrically-conductive resistance detected out of the second electrically-conductive pads. The resistance value of the third electrically-conductive resistance detected out of the second electrically-conductive pads is set equal to the resistance value of the fourth electrically-conductive resistance detected out of the fourth electrically-conductive pads.

Any positions can be set on the electrically-insulating substrate relative to a first plane determined based on the first and second electrically-conductive resistances and a second plane determined based on the third and fourth electrically-conductive resistances with a higher accuracy. If electrically-conductive pads are positioned based on the set positions, a chip can reliably be mounted on the printed wiring board with a higher positional accuracy. This contributes to a closed-packed arrangement or higher density of the electrically-conductive pads. Mounting efficiency can be improved.

The terminal pad may comprise: a first electrically-conductive layer extending over the substrate; a substitution layer extending over the surface of the first electrically-conductive layer, the substitution layer made of a material inducing substitution reaction to a given metal; and a plating film received on the surface of the substitution layer, the plating film made of the given metal. In this case, the first to fourth electrically-conductive resistances may comprise: a substitution layer extending over the substrate, the substitution layer made of said material; and a plating film received on the surface of the substitution layer, the plating film made of the given metal.

A specific method of forming a plating film may be provided to realize the aforementioned method of making the printed wiring board. The method of making a plating film, may comprise: forming a resist film of a first pattern on an electrically-insulating plate; forming a plating film of a metal material on the electrically-insulating plate based on the first pattern after formation of the resist film; removing the resist film of the first pattern; and forming a plating film of the metal material based on the first pattern and a second pattern different from the first pattern after removal of the resist film.

The method enables establishment of the electrically-conductive resistance thinner than the terminals. Reduction of the electrically-conductive resistance reliably induces a larger increase in the resistance value. Accordingly, the contour can be defined with a higher accuracy. To the contrary, if the thickness of the electrically-conductive resistance is set larger, only a smaller increment of the resistance value can be achieved for the reduction of the substrate. It is difficult to detect the resistance value with high accuracy.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will become apparent from the following description of the preferred embodiment in conjunction with the accompanying drawings, wherein:

FIG. 1 is a side view of an electronic component package according to an embodiment of the present invention;

FIG. 2 is a plan view schematically illustrating the structure of the printed wiring board of the electronic component package;

FIG. 3 is an enlarged plan view of a first electrically-conductive resistance;

FIG. 4 is an enlarged vertical sectional view of an electrically-conductive pad;

FIG. 5 is an enlarged vertical sectional view of the electrically-conductive resistance;

FIG. 6 is an enlarged partial side view schematically illustrating the structure of a grinding apparatus;

FIG. 7 is a sectional view of an electrically-insulating plate in a method of making a substrate material;

FIG. 8 is a sectional view of the electrically-insulating plate in a process of forming a via hole;

FIG. 9 is a sectional view of the electrically-insulating plate in a process of forming a seed layer;

FIG. 10is a sectional view of the electrically-insulating plate in a process of forming a resist film;

FIG. 11 is a sectional view of the electrically-insulating plate in a process of forming a plating film in a first pattern;

FIG. 12 is a sectional view of the electrically-insulating plate in a process of forming a resist film;

FIG. 13 is a sectional view of the electrically-insulating plate after removal of the resist film;

FIG. 14 is a sectional view of the electrically-insulating plate in a process of forming a plating film in the first and second patterns; and

FIG. 15 is an enlarged partial sectional side view schematically illustrating the electronic component package mounted on a motherboard.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 schematically illustrates an electronic component package 11 according to an embodiment of the present invention. The electronic component package 11 includes a small-sized printed wiring board 12. A semiconductor chip 13 is mounted on the printed wiring board 12. A ball grid array 14 is formed on the semiconductor chip 13 for mounting the semiconductor chip 13 on the printed wiring board 12. The ball grid array 14 is composed of spherical electrically-conductive terminals 15 arranged in accordance with a given pattern. The individual electrically-conductive terminals 15 are received on corresponding terminal pads or electrically-conductive pads 16 on the printed wiring board 12. The electrically-conductive pads 16 may be connected to electrically-conductive lands 17 located at the back surface of the printed wiring board 12. Vias, not shown, maybe employed to connect the electrically-conductive pads 16 and the electrically-conductive lands 17, for example. Electronic elements such as condensers 18 and capacitors 19 may be mounted on the printed wiring board 12 in addition to the semiconductor chip 13.

As shown in FIG. 2, the printed wiring board 12 includes an electrically-insulating substrate 21. A ceramic material or a resin material may be employed to form the substrate 21, for example. The substrate 21 is formed in a tetragonal shape. A first contour 24 is defined in the substrate 21 to extend along or in parallel with a first imaginary plane 22. A second contour 25 is likewise defined in the substrate 21 to extend along or in parallel with a second imaginary plane 23 orthogonal to the first imaginary plane 22.

First and second electrically-conductive resistances 26, 27 are located on the substrate 21 along the first contour 24. The first and second electrically-conductive resistances 26, 27 are spaced away from each other. Likewise, third and fourth electrically-conductive resistances 28, 29 are located on the substrate 21 along the second contour 25. The third and fourth electrically-conductive resistances 28, 29 are spaced away from each other.

As shown in FIG. 3, for example, the first electrically-conductive resistance 26 defines its contour along a pair of reference line 31, 31 orthogonal to the first plane 22. The reference lines 31 extend in parallel with the second plane 23. The interval is set at a given value W between the reference lines 31, 31. As mentioned above, the first electrically-conductive resistance 26 defines its front end along the first plane 22 or first contour 24. On the other hand, the first electrically-conductive resistance 26 defines its rear end along a reference line 32 extending in parallel with the first plane 22. The interval is set at a given value L between the first plane 22 and the reference line 32.

A pair of longitudinal electrically-conductive pattern 33, 33 is connected to the rear end of the first electrically-conductive resistance 26. The individual longitudinal electrically-conductive pattern 33 extends on a straight line along the reference line 31. Output electrically-conductive pads 34, 34 are connected to the rear end of the longitudinal electrically-conductive patterns 33, 33. The longitudinal electrically-conductive patterns 33 and the output electrically-conductive pads 34 are formed on the substrate 21. The resistance value is detected out of the electrically-conductive pads 34, 34 for the first electrically-conductive resistance 26. The detected resistance value is set at a given value.

Here, the second, third and fourth electrically-conductive resistances 27, 28, 29 may have structures identical to that of the first electrically-conductive resistance 26. In this case, the second electrically-conductive resistance 27 may have a structure identical to at least that of the first electrically-conductive resistance 26. The fourth electrically-conductive resistance 29 may have a structure identical to at least that of the third electrically-conductive resistance 28. In other words, the resistance value of the second electrically-conductive resistance 27 may be set equal to at least the resistance value of the first electrically-conductive resistance 26, while the resistance value of the fourth electrically-conductive resistance 29 may be set equal to at least the resistance value of the third electrically-conductive resistance 28.

As is apparent from FIG. 4, for example, the individual electrically-conductive pad 16 has a multilayered structure. Specifically, the individual electrically-conductive pad 16 includes a first electrically-conductive layer 35 extending on the substrate 21. The first electrically-conductive layer 35 may be made of a metallic material such as copper, for example. The first electrically-conductive layer 35 may be integral to the aforementioned electrically-conductive land 17 through a via 36, for example.

A so-called substitution layer 37 extends on the surface of the first electrically-conductive layer 35. The substitution layer 37 is made of a material inducing substitution reaction to a specific metallic material. Such a material includes nickel inducing substitution reaction to gold, for example.

A plating layer 38 is received on the surface of the substitution layer 37. The plating layer 38 may be made of a metallic material having a particularly higher electrically-conductivity. Such a metallic material includes gold, for example. If other material is employed to form the plating layer 38 in place of gold, the material of the aforementioned substitution layer 37 may be selected in accordance with the other material. The electrically-conductive terminal 15 is bonded to the plating layer 38.

As is apparent from FIG. 5, the individual electrically-conductive resistance 26, 27, 28, 29 includes a substitution layer 39 extending on the substrate 21. The substitution layer 39 is made of the material utilized in the aforementioned substitution layer 37. A plating layer 41 is received on the surface of the substitution layer 39. The plating layer 41 is made of the material utilized in the aforementioned plating layer 38.

Next, a detailed description will be made on a method of making the printed wiring board 12. A substrate material corresponding to the substrate 21 is first prepared. The electrically-conductive pads 16, the condensers 18, the capacitors 19 and the first to fourth electrically-conductive resistances 26, 27, 28, 29 are formed in individual sections on the substrate material. In addition, the longitudinal electrically-conductive patterns 33 and the output electrically-conductive pads 34 are formed for the individual electrically-conductive resistances 26, 27, 28, 29. The individual sections correspond to the individual printed wiring boards 12. In other words, the one-piece substrate material is divided into the printed wiring boards 12.

Grinding process is then effected on the individual printed wiring board 12 after the division. The grinding process serves to form the first and second contours 24, 25 in the substrate 21. As shown in FIG. 6, for example, a grinding apparatus 42 is utilized in the grinding process.

The grinding apparatus 42 includes a lapping faceplate 44 defining a flat surface. An abrasive is supplied to the flat surface 43of the lapping faceplate 44, for example. The abrasive agent may be made of a fluid and grains dispersed in the fluid, for example.

A pair of holder member 45, 45 is opposed to the flat surface 43 of the lapping faceplate 44, for example. The printed wiring board 12 is held between the holder members 45, 45. The substrate 21 is thus kept in an attitude perpendicular to the flat surface 43 of the lapping faceplate 44. The flat surface 43 of the lapping faceplate 44 is allowed to move relative to the printed wiring board 12.

A pressure mechanism 46 is related to the holder members 45. The pressure mechanism 46 includes a pair of urging member 47, 47, for example. The individual urging member 47 is coupled to the holder members 45 outside the printed wiring board 12, for example. The urging members 47 serve to exert an urging force on the printed wiring board 12. The urging force serves to urge the printed wiring board 12 against the flat surface 43 of the lapping faceplate 44. The grinding process is in this manner effected.

A resistance measuring apparatuses 48 are connected to the printed wiring board 12 on the holder members 45. The resistance measuring apparatus 48 is designed to supply an electric current for measurement from given contacts 49. The current and voltage values of the supplied current are utilized to calculate resistance values. The contacts 49 of the resistance measuring apparatus 48 contact the output electrically-conductive pads 34 of the electrically-conductive resistances 26, 27, 28, 29. The contacts 49 of the resistance measuring apparatus 48 may be embedded in the holder member 45, for example. According to this structure, the contacts 49 of the resistance measuring apparatus 48 contact the output electrically-conductive pads 34 when the printed wiring board 12 is held between the holder members 45, 45.

A controller circuit 51 is incorporated in the grinding apparatus 42. The controller circuit 51 is allowed to control the urging force of the individual urging member 47 based on the resistance value supplied from the resistance measuring apparatus 48. The controller circuit 51 refers to a reference value of the resistance value stored in a memory 52, for example. The size of the individual electrically-conductive resistance 26, 27, 28, 29 is set in a predetermined size based on the reference value of the resistance value.

Now, assume that the first contour 24 is formed with the grinding apparatus 42. The first contour 24 of the substrate 21 is urged against the flat surface 43 of the lapping faceplate 44. The controller circuit 51 instructs the resistance measuring apparatuses 48, 48 to measure resistance values. The resistance measuring apparatuses 48, 48 measure the resistance values of the first and second electrically-conductive resistances 26, 27. The resistance values of the first and second electrically-conductive resistances 26, 27 respectively increase in response to reduction of the first and second electrically-conductive resistances 26, 27.

The controller circuit 51 separately controls the urging force of the first and second urging members 47, 47 until the resistance value of the first and second electrically-conductive resistances 26, 27 simultaneously reach a target value. Specifically, if the resistance value of the first electrically-conductive resistance 26 is smaller than that of the second electrically-conductive resistance 27, for example, the controller circuit 51 operates to increase the urging force of the urging member 47 closer to the first electrically-conductive resistance 26. To the contrary, if the resistance value of the second electrically-conductive resistance 27 is smaller than that of the first electrically-conductive resistance 26, the controller circuit 51 operates to increase the urging force of the urging member 47 closer to the second electrically-conductive resistance 27. The controller circuit 51 outputs a given control signal to power sources of the urging members 47 for controlling the increase of the urging force. The resistance values of the first and second electrically-conductive resistances 26, 27 are thus set at an equal value. As a result, the shapes of the first and second electrically-conductive resistances 26, 27 become isomorphic. The aforementioned target value is set smaller than the reference value.

When the resistance value of the first electrically-conductive resistance 26 coincides with that of the second electrically-conductive resistance 27 in the aforementioned manner, the controller circuit 51 keeps equally increase the urging forces of the urging members 47, 47. The controller circuit 51 keeps comparing the resistance values of the first and second electrically-conductive resistances 26, 27 with the reference value, respectively, during the increase of the urging forces. The controller circuit 51 serves to release the urging members 47 from the application of the urging forces when the resistance values of the first and second electrically-conductive resistances 26, 27 are simultaneously set equal to the reference value. The first and second electrically-conductive resistances 26, 27 are in this manner formed into a predetermined shape. The first contour 24 of the substrate 21 is allowed to extend straight.

When the first contour 24 has been established in the aforementioned manner, the second contour 25 is subsequently subjected to the grinding process. Here, since the aforementioned grinding process is repeated, the third and fourth electrically-conductive resistances 28, 29 are formed into a predetermined shape. The second contour 25 of the substrate 21 is allowed to extend straight. In addition, the second contour 25 is set perpendicular to the first contour 24 in the substrate 21 based on the location of the first to fourth electrically-conductive resistances 26, 27, 28, 29.

Next, a brief description will be made on a method of making the aforementioned substrate material. As shown in FIG. 7, an electrically-insulating plate 54 made of a ceramic is prepared, for example. The electrically-conductive lands 17 are formed on the back surface of the electrically-insulating plate 54. As shown in FIG. 8, via holes 55 are then bored from the surface of the electrically-insulating plate 54 at positions corresponding to the electrically-conductive lands 17. The via holes 55 penetrate through the electrically-insulating plate 54. The upper surface of the electrically-conductive land 17 is exposed within the via hole 55.

As shown in FIG. 9, a seed layer 56 made of copper is then formed over the entire surface of the electrically-insulating plate 54. Plating may be employed to form the seed layer 56, for example. The surface of the electrically-insulating plate 54 is first subjected to roughening process in advance of the formation of the seed layer 56. The roughening process serves to promote the growth of the seed layer 56.

As shown in FIG. 10, a resist film 57 is formed in a first pattern on the seed layer 56. The resist film 57 surrounds the contours of wiring patterns such as the electrically-conductive pads 16, for example. The resist film 57 forms voids 58 above the via holes 55. As shown in FIG. 11, a plating film made of copper is thereafter formed based on the resist film 57. The plating film grows from the exposed seed layer 56 outside the resist film 57. The via holes 55 are thus filled in with the copper. At the same time, the first electrically-conductive layers 35 of the electrically-conductive pads 16 are formed on the via holes 55. The resist film 57 is then removed.

As shown in FIG. 12, resist films 59 are formed in a second pattern on the electrically-insulating plate 54 after the removal of the resist film 57. The shapes of the resist films 59 reflect the shapes of the first to fourth electrically-conductive resistances 26, 27, 28, 29 in the second pattern. All the resist films 59 have an equal shape. Specifically, the first to fourth electrically-conductive resistances 26, 27, 28, 29 have an equal shape. Etching process is then effected based on the resist films 59. As shown in FIG. 13, the seed layer 56 is removed outside the resist film 59. The seed layer 56 remains below the resist films 59. Although the etching process serves to remove not only the seed layer 56 but also a part of the first electrically-conductive layer 35, the first electrically-conductive layer 35 of a given thickness remains on the seed layer 56. The resist film 59 is then removed.

As shown in FIG. 14, a plating film of a metal material is formed after the removal of the resist film 59. Here, electroless plating is effected to deposit nickel and gold. A substitution reaction liquid containing nickel is employed to form a plating film made of gold. In other words, nickel or substitution layers 37, 39 are first formed on the seed layer 56 and the first electrically-conductive layers 35. The substitution reaction is then caused between the nickel in the substitution layer 37, 39 and the gold. The plating films 38, 41 made of gold are thus formed on the surfaces of the substitution layers 37, 39 made of nickel.

The aforementioned method enables an accurate positioning of the electrically-conductive resistances 26, 27, 28, 29 relative to the electrically-conductive pads 16. The first and second contours 24, 25 are defined based on the electrically-conductive pads 26, 27, 28, 29 so that the first and second contours 24, 25 are positioned with high accuracy relative to the electrically-conductive pads 16. The first contour 24 is thus reliably set perpendicular to the second contour 25 with high accuracy. The electrically-conductive pads 16 are in this manner positioned at locations spaced from the first and second contours 24, 25 by set distances.

In addition, the aforementioned method enables establishment of the electrically-conductive resistances 26, 27, 28, 29 thinner than the electrically-conductive pads 16. Reduction of the electrically-conductive resistances 26, 27, 28, 29 in the aforementioned manner reliably induces a larger increase in the resistance value. Accordingly, the first and second contours 24, 25 can be defined with high accuracy. To the contrary, if the thickness of the electrically-conductive resistance is set larger, only a smaller increment of the resistance value can be achieved for the reduction of the substrate 21. It is difficult to detect the resistance value with high accuracy.

Now, assume that the aforementioned electronic component package 11 is mounted on a large-sized printed circuit board such as a motherboard, for example. As shown in FIG. 15, a socket 63 is mounted on a printed wiring board 62 in the motherboard 61. Screws 64 may be employed to attach the socket 63 to the printed wiring board 62, for example. The socket 63 includes a support plate 65 extending in parallel with the surface of the printed wiring board 62. Electrically-conductive terminals 66 are supported on the support plate 65. When the socket 63 is mounted on the printed wiring board 62, the individual electrically-conductive terminal 66 is received on a corresponding electrically-conductive land 67 formed on the printed wiring board 62. Electrical connection is established between the electrically-conductive terminals 66 and the electrically-conductive lands 67.

A depression 68 is formed in the socket 63 so as to receive the electronic component package 11. A step 69 is defined in the depression 68 along a horizontal plane extending in parallel with the surface of the printed wiring board 62. The depression 68 is designed to receive the printed wiring board 12 of the electronic component package 11 at the step 69. The opening of the depression 68 corresponds to the contour of the printed wiring board 12. The opening thus serves to position the printed wiring board 12 on the step 69 with high accuracy. When the printed wiring board 12 is received on the step 69 within the depression 68, the back surface of the printed wiring board 12 is opposed to the support plate 65 of the socket 63.

When the printed wiring board 12 is received on the step 69, the electrically-conductive lands 17 are received on the corresponding electrically-conductive terminals 66. Electrical connection is thus established between the electrically-conductive lands 17 and the electrically-conductive terminals 66. In this case, the electrically-conductive lands 17 can likewise reliably be positioned with a higher accuracy relative to the first and second contours 24, 25 of the printed wiring board 12 in the aforementioned electronic component 11. An accurate positioning of the electrically-conductive lands 17 relative to the first and second contours 24, 25 in this manner enables a reliable contact between the electrically-conductive lands 17 and the corresponding electrically-conductive terminals 66, even if the interval is shortened between the adjacent electrically-conductive lands 17 or between the adjacent electrically-conductive terminals 66. A so-called land grid array (LGA) is thus established.

In addition, two or more of the semiconductor chip 13 may be mounted on the aforementioned printed wiring board 12. Other process such as cutting process or the like, in place of the aforementioned grinding process, may be employed to form the first and second contours 24, 25 of the substrate 21. 

1. A method of making a printed wiring board, comprising: supplying a current to first and second electrically-conductive resistances located away from each other on a straight line defined on an electrically-insulating substrate; detecting resistance values of the first and second electrically-conductive resistances based on the current; and forming a contour of the substrate along the straight line based on the resistance values.
 2. The method according to claim 1, wherein the first and second electrically-conductive resistances are contoured in an identical shape in advance of forming said contour.
 3. The method according to claim 1, wherein the resistance value of the first electrically-conductive resistance is compared with a predetermined reference value in forming said contour.
 4. A method of making a printed wiring board, comprising: supplying a current to first and second electrically-conductive resistances located away from each other on a first straight line defined on an electrically-insulating substrate; detecting resistance values of the first and second electrically-conductive resistances based on the current; forming a first contour of the substrate along the first straight line based on the resistance values from the first and second electrically-conductive resistances; supplying a current to third and fourth electrically-conductive resistances located away from each other on a second straight line orthogonal to the first straight line defined on the electrically-insulating substrate; detecting resistance values of the third and fourth electrically-conductive resistances based on the current; and forming a second contour of the substrate along the second straight line based on the resistance values from the third and fourth electrically-conductive resistances.
 5. The method according to claim 4, wherein the first and second electrically-conductive resistances are contoured in an identical shape in advance of forming said first contour.
 6. The method according to claim 4, wherein the resistance values of the first and third electrically-conductive resistances are compared with predetermined reference values in forming said first and second contours.
 7. A printed wiring board, comprising: an electrically-insulating substrate having first and second contours defined along imaginary planes orthogonal to each other: an electrically-conductive terminal pad formed on the substrate; a first electrically-conductive resistance formed on the substrate along the first contour; a pair of first electrically-conductive pads formed on the substrate, the first electrically-conductive pads connected to the first electrically-conductive resistance; a second electrically-conductive resistance formed on the substrate along the first contour away from the first electrically-conductive resistance; a pair of second electrically-conductive pads formed on the substrate, the second electrically-conductive pads connected to the second electrically-conductive resistance; a third electrically-conductive resistance formed on the substrate along a second contour; a pair of third electrically-conductive pads formed on the substrate, the third electrically-conductive pads connected to the third electrically-conductive resistance; a fourth electrically-conductive resistance formed along the second contour away from the third electrically-conductive resistance on the substrate; and a pair of fourth electrically-conductive pads formed on the substrate, the fourth electrically-conductive pads connected to the fourth electrically-conductive resistance, wherein resistance value of the first electrically-conductive resistance detected out of the first electrically-conductive pads is set equal to resistance value of the second electrically-conductive resistance detected out of the second electrically-conductive pads, and resistance value of the third electrically-conductive resistance detected out of the second electrically-conductive pads is set equal to resistance value of the fourth electrically-conductive resistance detected out of the fourth electrically-conductive pads.
 8. The printed wiring board according to claim 7, wherein said terminal pad comprises: a first electrically-conductive layer extending over the substrate; a substitution layer extending over a surface of the first electrically-conductive layer, the substitution layer made of a material inducing substitution reaction to a given metal; and a plating film received on a surface of the substitution layer, the plating film made of said given metal.
 9. The printed wiring board according to claim 8, wherein said first to fourth electrically-conductive resistances comprise: a substitution layer extending over said substrate, the substitution layer made of said material; and a plating film received on a surface of the substitution layer, the plating film made of said given metal.
 10. A method of making a plating film, comprising: forming a resist film of a first pattern on an electrically-insulating plate; forming a plating film of a metal material on the electrically-insulating plate based on the first pattern after formation of the resist film; removing the resist film of the first pattern; and forming a plating film of the metal material based on the first pattern and a second pattern different from the first pattern after removal of the resist film. 